LTM4658EVPBF datasheet(11/26 Pages) AD

11 / 26 page

LTM4658

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

AGND allows the MODE/SYNC to be floating. Please note

that low switching frequency will increase the inductor

peak current and the output voltage ripple.

Multiphase Operation

For output loads that demand more than 10A of current,

multiple LTM4658s can be paralleled to run out of phase

to provide more output current without increasing input

and output voltage ripples. See Table 3.

ToparallelmultipleLTM4658modulestoachievethesame

switching frequency, a perfect interleaved phase shift and

an accurate current sharing between different modules,

one of the LTM4658 will become the master module

and the rest of LTM4658s need to be programmed to be

slave modules. Refer to multiphase application circuits.

1. Connect a resistor from FREQ pin to AGND of the mas-

ter phase will programs the frequency and configures

the MODE/SYNC pin to become a clock output used to

drive the MODE/SYNC pins of the slave phase(s).

Connecting the FREQ pin of the master phase to VIN

configures the MODE/SYNC pin to become an input

capable of accepting an external clock. The switching

frequency defaults to the nominal 2MHz internal fre-

quency when the external clock is unavailable, such as

during start-up.

Connecting the FB pin to VIN configures a phase as a

slave. The MODE/SYNC becomes an input and the volt-

age control loop is disabled. The slave phase current

control loop is still active and the peak current is con-

trolled via the shared COMP node. Careful consideration

should be taken when routing the COMP node between

phases. Routing the COMP and AGND nodes together

is recommended to create a low inductance path.

Connecting the PGOOD pins together and adding an

external pull-up resistor allows the master phase to

communicate with the slave phases on when start-up

has been completed.

2. The phasing of a slave phase relative to the master

phase is programmed with a resistor divider on the

FREQ pin (see Figure 2). Use of 1% resistors is recom-

mended. See Table 4 for more information.

Table 3. Multiphase Configuration

MASTER/SLAVE

FREQ PIN

FB PIN

MODE/SYNC PIN

SWITCHING FREQUENCY (fSW)

Master

VIN

VOUT Divider

Clock Input

External Clock/2MHz Default

Master

Resistor to AGND

VOUT Divider

Clock Output

FREQ Programmed

Slave

VIN Divider

VIN

Clock Input

External Clock

Table 4. Programming Slave Phase Angle

SYNC PHASE ANGLE

RATIO

EXAMPLE

0°

0Ω

90°

3 • R

301k

100k

120°

7 • R

5 • R

243k

174k

180°

0Ω

240°

5 • R

7 • R

174k

243k

270°

3 • R

100k

300k

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