ADL5354ACPZ-R7 datasheet(17/24 Pages) AD

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Data Sheet

ADL5354

Rev. A | Page 17 of 24

The performance of this amplifier is critical in achieving a high

intercept passive mixer without degrading the noise floor of the

system. This is a critical requirement in an interferer rich

environment, such as cellular infrastructure, where blocking

interferers can limit mixer performance. The bandwidth of the

intermodulation performance is somewhat influenced by the

current in the LO amplifier chain. For dc current sensitive

applications, it is permissible to reduce the current in the LO

amplifier by raising the value of the external bias control resistor.

For dc current critical applications, the LO chain can operate

with a supply voltage as low as 3.3 V, resulting in substantial

dc power savings.

In addition, when operating with supply voltages below 3.6 V, the

ADL5354 has a power-down mode that permits the dc current

to drop to approximately 300 µA.

The logic inputs are designed to work with any logic family that

provides a Logic 0 input level of less than 0.4 V and a Logic 1

input level that exceeds 1.4 V. All logic inputs are high impedance

up to Logic 1 levels of 3.3 V. At levels exceeding 3.3 V, protection

circuitry permits operation up to 5.5 V, although a small bias

current is drawn.

All pins, including the RF pins, are ESD protected and have

been tested to a level of 1500 V HBM and 500 V FICDM.

ADL5354ACPZ-R7 데이터시트(PDF) 17 Page - Analog Devices