7

www.pericom.com

PS9060A

08/23/11

PI3VDP411LSR

Dual Mode DisplayPort™ to DVI/HDMI™ Electrical Bridge (Level Shifter)

SR1

SR0

Rise/Fall Time (Typ)

1

1

140ps

1

0

130ps

0

1

120ps

0

0

110ps

Test Setup Condition

Rise/Fall time is from 20% to 80% on Rising/Falling edge

Date rate: 620 Mbps

Input: 1V differential peak-to-peak clock pattern

Equalization : 3dB

Table 1: OE Pin Description

OE#

Device State

Comments

Asserted (low voltage)

Differential input buffers and output buffers

enabled. Input impedance = 50Ω

Normal functioning state for IN_D to OUT_D

level shifting function.

Unasserted (high voltage)

Low-power state.

à

Differential input buffers and termination

are disabled.

à

Differential inputs are in a high

impedance state.

à

OUT_D level-shifting outputs are

disabled.

à

OUT_D level-shifting outputs are in high

impedance state.

à

Internal bias currents are turned off.

Intended for lowest power condition when:

à

No display is plugged in or

à

The level shifted data path is disabled

HPD_SINK input and HPD_SOURCE

output are not affected by OE# SCL_

SOURCE, SCL_SINK, SDA_SOURCE

and SDA_SINK signals and functions

are not affected by OE#

11-0084