71M6543GHT datasheet(42/75 Pages) MAXIM

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71M6543FT/71M6543HT/

71M6543GT/71M6543GHT

Energy Meter ICs

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In LCD mode, the data contained in the LCD_SEG reg-

isters is displayed using the segment driver pins. Up to

two LCD segments connected to the pins SEGDIO22 and

SEGDIO23 can be made to blink without the involvement

of the MPU, which is disabled in LCD mode. To minimize

battery power consumption, only segments that are used

should be enabled.

After the transition from LCD mode to MSN or BRN mode,

the PC (Program Counter) is at 0x0000, the XRAM is in

an undefined state, and configuration I/O RAM bits are

reset (see Table 12) for I/O RAM state upon wake). The

data stored in nonvolatile I/O RAM locations is preserved

in LCD mode (the shaded locations in Table 12 are non-

volatile).

Sleep Mode

When the VV3P3SYS pin voltage drops below 2.8 VDC,

the 71M654xT enters BRN mode and the VV3P3D pin

obtains power from the VBAT pin instead of the VV3P3SYS

pin. Once in BRN mode, the MPU may invoke SLP mode

by setting the SLEEP bit. The purpose of SLP mode is to

consume the least amount power while still maintaining

the real time clock, temperature compensation of the

RTC, and the nonvolatile portions of the I/O RAM.

In SLP mode, the VV3P3D pin is disconnected, removing

all sources of current leakage from the VBAT pin. The

nonvolatile I/O RAM locations and the SLP mode functions,

such as the temperature sensor, oscillator, RTC, and the

RTC temperature compensation are powered by the

VBAT_RTC pin. SLP mode can be exited only by a system

power-up event or one of the wake methods.

If the SLEEP bit is asserted when VV3P3SYS pin power is

present (i.e., while in MSN mode), the 71M654xT enters

SLP mode, resetting the internal WAKE signal, at which

point the 71M654xT begins the standard wake from sleep

procedures.

When power is restored to the VV3P3SYS pin, the

71M654xT transitions from SLP mode to MSN mode and

the MPU PC (Program Counter) is initialized to 0x0000.

At this point, the XRAM is in an undefined state, but

nonvolatile I/O RAM locations are preserved.

Figure 10. Typical Current-Sense Circuit Using Current Transformer in a Single-Ended Configuration

Figure 9. Typical Voltage Sense Circuit Using Resistive Divider

RIN

VIN

V3P3A

ROUT

VOUT

IOUT

IAP

V3P3A

1:N

IIN

RBURDEN

NOISE FILTER

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