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PI6CFGL202BLIEX 데이터시트(PDF) 2 Page - Diodes Incorporated

부품명 PI6CFGL202BLIEX
상세설명  Low Power PCIe 3.0 Clock Generator with 2 HCSL Outputs
PDF  9 Pages
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제조업체  DIODES [Diodes Incorporated]
홈페이지  http://www.diodes.com
Logo DIODES - Diodes Incorporated

PI6CFGL202BLIEX 데이터시트(HTML) 2 Page - Diodes Incorporated

  PI6CFGL202BLIEX Datasheet HTML 1Page - Diodes Incorporated PI6CFGL202BLIEX Datasheet HTML 2Page - Diodes Incorporated PI6CFGL202BLIEX Datasheet HTML 3Page - Diodes Incorporated PI6CFGL202BLIEX Datasheet HTML 4Page - Diodes Incorporated PI6CFGL202BLIEX Datasheet HTML 5Page - Diodes Incorporated PI6CFGL202BLIEX Datasheet HTML 6Page - Diodes Incorporated PI6CFGL202BLIEX Datasheet HTML 7Page - Diodes Incorporated PI6CFGL202BLIEX Datasheet HTML 8Page - Diodes Incorporated PI6CFGL202BLIEX Datasheet HTML 9Page - Diodes Incorporated  
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www.diodes.com
May 2018
Diodes Incorporated
PI6CFGL202B
Document Number DS41024 Rev 1-2
A product Line of
Diodes Incorporated
PI6CFGL202B
Pin Description
Pin # Pin Name
Type
Description
1
S0
Input
Select pin 0 (Internal pull-up resistor). See Table 1.
2
S1
Input
Select pin 1 (Internal pull-up resistor). See Table 1.
3
SS0
Input
Spread Select pin 0 (Internal pull-up resistor). See Table 2.
4
XTAL_IN
Input
Crystal or clock input. Connect to a 25MHz crystal or single ended clock.
5
XTAL_OUT
Output
Crystal connection. Leave unconnected for clock input.
6
OE
Input
Output enable. Internal pull-up resistor.
7
GNDX
Power
Crystal ground pin.
8
SS1
Input
Spread Select pin 1 (Internal pull-up resistor). See Table 2.
9
VDDDIG3.3
Power
3.3V digital power.
10
CLK1#
Output
HCSL compliment clock output, LOW when output is disabled.
11
CLK1
Output
HCSL clock output, LOW when output is disabled.
12
VDDO
Power
Power supply, nominal 1.8V, range1.05V~3.3V.
13
GNDA
Power
Output and analog circuit ground.
14
CLK0#
Output
HCSL compliment clock output, LOW when output is disabled.
15
CLK0
Output
HCSL clock output, LOW when output is disabled.
16
VDDA3.3
Power
3.3V power supply for PLL core.
Table 1: Frequency Select Table
S1
S0
CLK(MHz)
0
0
25
0
1
100
1
0
125
1
1
200
Table 2: Spread Selection Table
SS1
SS0
Spread
0
0
No Spread
0
1
Down -0.5
1
0
Down -0.75
1
1
No Spread



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