ADP1031ACPZ-4-R7 datasheet(3/38 Pages) AD

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Data Sheet

ADP1031

Rev. A | Page 3 of 38

SPECIFICATIONS

VINP voltage (VINP) = 24 V, MVDD voltage (VMVDD) = 3.3 V, SVDDx voltage (VSVDDx) = 3.3 V, VOUT1 voltage (VOUT1) = 24 V, VOUT2

voltage (VOUT2) = 5.15 V, VOUT3 voltage (VOUT3) = −15 V, and TA = 25°C for typical specifications. Minimum and maximum specification

apply over the entire operating range of 4.5 V ≤ VINP ≤ 60 V, 2.3 V ≤ VMVDD ≤ 5.5 V, 1.8 V ≤ VSVDDx ≤ 5.5 V, and −40°C ≤ TJ ≤ +125°C,

unless otherwise noted.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT SUPPLY VOLTAGE RANGE

VINP

4.5

MVDD

VMVDD

2.3

5.5

SVDDx

VSVDDx

1.8

5.5

Applies to SVDD1 and SVDD2

OUTPUT POWER AND EFFICIENCY

Transformer = 750316743

Total Output Power

1720

VOUT1 current (IOUT1) = 70 mA,

VOUT2 current (IOUT2) = 7 mA,

VOUT3 current (IOUT3) = −0.3 mA

520

IOUT1 = 20 mA, IOUT2 = 7 mA,

IOUT3 = −0.3 mA

Efficiency

88.8

IOUT1 = 70 mA, IOUT2 = 7 mA,

IOUT3 = −0.3 mA

84.8

IOUT1 = 20 mA, IOUT2 = 7 mA,

IOUT3 = −0.3 mA

Power Dissipation

216.5

IOUT1 = 70 mA, IOUT2 = 7 mA,

IOUT3 = −0.3 mA

93.1

IOUT1 = 20 mA, IOUT2 = 7 mA,

IOUT3 = −0.3 mA

QUIESCENT CURRENT

VINP

Operating Current

IQ_VINP

1.77

Normal operation, VOUT1,

VOUT2, VOUT3 = no load

Shutdown Current

ISHDN_VINP

125

175

µA

EN voltage (VEN) = 0 V

MVDD

SPI Active Mode

IQ_MVDD(SPI_ACTIVE)

4.1

6.5

VIx1 = logic low, MSS = logic low

9.2

VIx1 = logic high, MSS = logic low

SPI Low Power Mode

IQ_MVDD(SPI_LOWPWR)

1.6

2.5

VIx1 = logic low, MSS = logic high

1.6

2.5

VIx1 = logic high, MSS = logic high

SVDD1

SPI Active Mode

IQ_SVDD1(SPI_ACTIVE)

1.8

2.7

VIx1 = logic low, SSS = logic low

5.7

8.6

VIx1 = logic high, SSS = logic low

SPI Low Power Mode

IQ_SVDD1(SPI_LOWPWR)

1.8

2.7

VIx1 = logic low, SSS = logic high

1.8

2.7

VIx1 = logic high, SSS = logic high

SVDD2

IQ_SVDD2

µA

VIx1 = logic low

2.5

VIx1 = logic high

UVLO

VINP

Relative to PGNDP

Rising Threshold

VUVLO_FLYBACK(RISE)

4.44

4.49

Falling Threshold

VUVLO_FLYBACK(FALL)

4.29

4.34

Hysteresis

100

MVDD

Relative to MGND

Rising Threshold

VUVLO_MVDD (RISE)

2.14

2.28

Falling Threshold

VUVLO_MVDD (FALL)

1.9

Hysteresis

140

ADP1031ACPZ-4-R7 데이터시트(PDF) 3 Page - Analog Devices

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