SiP12107

www.vishay.com

Vishay Siliconix

S20-0484-Rev. C, 29-Jun-2020

13

Document Number: 63395

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

Power-Saving Mode Operation

To further improve efficiency at light-load condition,

SiP12107 provides a set of innovative implementations to

eliminate LS recirculating current and switching losses. The

internal zero crossing detector (ZCD) monitors LX node

voltage to determine when inductor current starts to flow

negatively. In power saving mode (PSM), as soon as

inductor valley current crosses zero, the device first deploys

diode emulation mode by turning off LS FET. If load further

decreases,

switching

frequency

is

further

reduced

proportional to load condition to save switching losses while

keeping output ripple within tolerance. The switching

frequency is set by the controller to maintain regulation. At

zero load this frequency can go as low as hundreds of Hz.

Whenever fixed frequency PWM operation is required over

the entire load span, power saving mode feature can be

OUTPUT MONITORING AND PROTECTION FEATURES

Output Over-Current Protection (OCP)

SiP12107 has pulse-by-pulse over-current limit control. The

inductor valley current is monitored during LS FET turn-on

valley current is compared with internal threshold (5 A typ.)

to determine the threshold for OCP. If monitored current is

higher than threshold, HS turn-on pulse is skipped and LS

FET is kept on until the valley current returns below OCP

limit.

In the severe over-current condition, pulse-by-pulse current

limit eventually triggers output under-voltage protection

(UVP), which latches the device off to prevent catastrophic

thermal-related failure. UVP is described in the next section.

Figure 6 illustrates the OCP operation.

Fig. 6 - Over-Current Protection Illustration

Output Under-Voltage Protection (UVP)

20 μs, then UVP event is recognized and both HS and LS

MOSFETs are turned off. UVP latches the device off until

UVP is only active after the completion of soft-start

sequence.

Output Over-Voltage Protection (OVP)

For OVP implementation, output is monitored through FB

pin. After soft-start, if the voltage level at FB is above 20 %

(typ.), OVP is triggered with HS FET turning off and LS FET

turning on immediately to discharge the output. Normal

operation is resumed once FB voltage drops back to 0.6 V.





Over-Temperature Protection (OTP)

SiP12017 has internal thermal monitor block that turns off

both HS and LS FETs when junction temperature is above

160 °C (typ.). A hysteresis of 30 °C is implemented, so when

junction temperature drops below 130 °C, the device

restarts by initiating the soft-start sequence again.

Soft Startup

SiP12107

deploys

an

internally

regulated

soft-start

sequence to realize a monotonic startup ramp without any

regulation in 1 ms (typ.) with the reference going from 0 V to

output voltage.

During soft-start period, OCP is activated. OVP and

short-circuit protection are not active until soft-start is

complete.



GH

Skipped GH pulse