SP8531DS/01

SP8531 12-Bit Sampling Serial Out Analog to Digital Converter

© Copyright 1999 Sipex Corporation

8

TIMING CHARACTERISTICS

(Typical @ 25

°C with V

PARAMETER

MIN.

TYP.

MAX.

UNIT

COND.

Thoughput Time (tTP=tA+tC)

4.25

µs

Acquisition Time (tA) (2 SCLK Periods)

400

500

ns

Conversion Time (tC) (15 SCLK Periods)

3.75

µs

SCLK Low Pulse Width (tSKL)

110

125

ns

SCLK High Pulse Width (tSKH)

110

125

ns

SCLK Period (tSKT)

250

ns

Bus Access Time (tCBA)

51

ns

Bus Relinquish Time (tBR)

45

ns

Setup Time -SCLK Falling to CSN Falling (tCSSU)

0

ns

CSN Low Before SCLK Rises (tCS)

90

ns

SCLK Falling to Data Valid (tSD)

50

ns

CSN Falling to status Rising (tDCS)

69

ns

SCLK 17 Falling to Status Rising Free Run (tDSS)

70

ns

SCLK 16 Falling to Status Falling ( tDSE)

45

ns

Delay SD Low to initiate Conversion (tPU)

5

µs

Aperture Delay Slave-Mode (tAPC)

30

ns

Aperture Delay Free-Running Mode (tAPS)

35

ns