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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADPD4200 데이터시트(PDF) 86 Page - Analog Devices |
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ADPD4200 데이터시트(HTML) 86 Page - Analog Devices |
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86 / 93 page  Data Sheet ADPD4200 REGISTER DETAILS analog.com Rev. 0 | 86 of 93 Table 32. Register Details Addr Name Bits Bit Name Description Reset Access 10: modulate TIA_VREF = 0.8855 V. 11: modulate TIA_VREF = 1.265 V. [5:3] TIA_GAIN_CH2_x TIA Resistor Gain Setting for Channel 2. 0x0 R/W 000: 200 kΩ. 001: 100 kΩ. 010: 50 kΩ. 011: 25 kΩ. 100: 12.5 kΩ. [2:0] TIA_GAIN_CH1_x TIA Resistor Gain Setting for Channel 1. 0x0 R/W 000: 200 kΩ. 001: 100 kΩ. 010: 50 kΩ. 011: 25 kΩ. 100: 12.5 kΩ. 0x010D PATTERN_A [15:12] LED_DISABLE_x Four-Pulse LED Disable Pattern. Set to 1 to disable the LED pulse in the matching position in a group of four pulses. The LSB maps to the first pulse. 0x0 R/W 0x012D PATTERN_B 0x014D PATTERN_C 0x016D PATTERN_D [11:8] MOD_DISABLE_x Four-Pulse Modulation Disable Pattern. Set to 1 to disable the modulation pulse in the matching position in a group of four pulses. The LSB maps to the first pulse. 0x0 R/W 0x018D PATTERN_E 0x01AD PATTERN_F 0x01CD PATTERN_G [7:4] SUBTRACT_x Four-Pulse Subtract Pattern. Set to 1 to negate the math operation in the matching position in a group of four pulses. The LSB maps to the first pulse. 0x0 R/W 0x01ED PATTERN_H 0x020D PATTERN_I 0x022D PATTERN_J [3:0] REVERSE_INTEG_x Four-Pulse Integration Reverse Pattern. Set to 1 to reverse the integrator positive and/or negative pulse order in the matching position in a group of four pulses. The LSB maps to the first pulse. 0x0 R/W 0x024D PATTERN_K 0x026D PATTERN_L 0x0110 DATA_FORMAT_A [15:11] DARK_SHIFT_x Number of Bits to Shift the Dark Data to the Right Before Writing to the FIFO for Time Slot x. Selectable between 0 bits and 32 bits. 0x0 R/W 0x0130 DATA_FORMAT_B 0x0150 DATA_FORMAT_C 0x0170 DATA_FORMAT_D [10:8] DARK_SIZE_x Number of Bytes of Dark Data to be Written to the FIFO for Time Slot x. Selectable between 0 bytes and four bytes. 0x0 R/W 0x0190 DATA_FORMAT_E 0x01B0 DATA_FORMAT_F [7:3] SIGNAL_SHIFT_x Number of Bits to Shift the Signal Data to the Right Before Writing to the FIFO for Time Slot x. Selectable between 0 bits and 32 bits. 0x0 R/W 0x01D0 DATA_FORMAT_G 0x01F0 DATA_FORMAT_H 0x0210 DATA_FORMAT_I [2:0] SIGNAL_SIZE_x Number of Bytes of Signal Data to be Written to the FIFO for Time Slot x. Selectable between 0 bytes and four bytes. 0x3 R/W 0x0230 DATA_FORMAT_J 0x0250 DATA_FORMAT_K 0x0270 DATA_FORMAT_L 0x0112 DECIMATE_A [15:11] Reserved Write 0x0. 0x0 R 0x0132 DECIMATE_B [10:4] DECIMATE_FACTOR_x Decimate Sample Divider. Output data rate is sample rate ÷ (DECIMATE_FACTOR_x + 1). Decimate by 1 to 128. 0x0 R/W 0x0152 DECIMATE_C 0x0172 DECIMATE_D [3:0] DECIMATE_TYPE_x Decimation Type Select. 0x0 R/W 0x0192 DECIMATE_E 0: block sum, CIC first order. 0x01B2 DECIMATE_F 1: signal uses CIC second order. 0x01D2 DECIMATE_G 10: signal uses CIC third order. 0x01F2 DECIMATE_H 11: signal uses CIC fourth order. 0x0212 DECIMATE_I 100: reserved. 0x0232 DECIMATE_J |
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