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MCP7940N-E/MS 데이터시트(PDF) 5 Page - Microchip Technology

부품명 MCP7940N-E/MS
상세설명  Battery-Backed I2C Real-Time Clock/Calendar with SRAM
PDF  58 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP7940N-E/MS 데이터시트(HTML) 5 Page - Microchip Technology

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 2011-2022 Microchip Technology Inc. and its subsidiares
DS20005010J-page 5
MCP7940N
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): VCC = +1.8V to 5.5V TA = -40°C to +85°C
Extended (E): VCC = +1.8V to 5.5V TA = -40°C to +125°C
Param.
No.
Symbol
Characteristic
Minimum Typical Maximum Units
Conditions
1FCLK
Clock Frequency
—
—
100
kHz 1.8V
 VCC < 2.5V
—
—
400
kHz 2.5V
 VCC  5.5V
2THIGH
Clock High Time
4000
—
—
ns
1.8V
 VCC < 2.5V
600
—
—
ns
2.5V
 VCC  5.5V
3TLOW
Clock Low Time
4700
—
—
ns
1.8V
 VCC < 2.5V
1300
—
—
ns
2.5V
 VCC  5.5V
4TR
SDA and SCL Rise Time
——
1000
ns
1.8V
 VCC < 2.5V
(Note 1)
——
300
ns
2.5V
 VCC  5.5V
(Note 1)
5TF
SDA and SCL Fall Time
——
1000
ns
1.8V
 VCC < 2.5V
(Note 1)
——
300
ns
2.5V
 VCC  5.5V
(Note 1)
6THD:STA Start Condition Hold Time
4000
—
—
ns
1.8V
 VCC < 2.5V
600
—
—
ns
2.5V
 VCC  5.5V
7TSU:STA Start Condition Setup Time
4700
—
—
ns
1.8V
 VCC < 2.5V
600
—
—
ns
2.5V
 VCC  5.5V
8THD:DAT Data Input Hold Time
0
—
—
ns
Note 2
9TSU:DAT Data Input Setup Time
250
—
—
ns
1.8V
 VCC < 2.5V
100
—
—
ns
2.5V
 VCC  5.5V
10
TSU:STO Stop Condition Setup Time
4000
—
—
ns
1.8V
 VCC < 2.5V
600
—
—
ns
2.5V
 VCC  5.5V
11
TAA
Output Valid From Clock
—
—
3500
ns
1.8V
 VCC < 2.5V
——
900
ns
2.5V
 VCC  5.5V
12
TBUF
Bus free time: Time the bus
must be free before a new
transmission can start
4700
—
—
ns
1.8V
 VCC < 2.5V
1300
—
—
ns
2.5V
 VCC  5.5V
13
TSP
Input Filter Spike Suppression
(SDA and SCL pins)
—
—
50
ns
Note 1
14
TFVCC
VCC fall time
300
—
—
s
Note 1
15
TRVCC
VCC rise time
0
—
—
s
Note 1
16
FOSC
Oscillator frequency
—
32.768
—
kHz
17
TOSF
Oscillator timeout period
1
—
—
ms
Note 1
Note 1: Not 100% tested.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.



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