CYT4BFCCJS datasheet(13/217 Pages) INFINEON

13 / 217 page

Datasheet

13 of 217

002-21617 Rev. *J

2022-02-18

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Functional description

3.2

System resources

3.2.1

Power system

The power system ensures that the supply voltage levels meet the requirements of each power mode, and

provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip

reset during the initial power ramp.

Three BOD circuits monitor the external supply voltages (VDDD, VDDA, VCCD). The BOD on VDDD and VCCD is initially

enabled and cannot be disabled. The BOD on VDDA is initially disabled and can be enabled by the user. For the

external supplies VDDD and VDDA, BOD circuits are software-configurable with two settings; a 2.7-V minimum

voltage that is robust for all internal signaling, and a 3.0-V minimum voltage, which is also robust for all I/O

specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety measure and is not a

robust detector.

Three over-voltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA, VCCD), and

overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD and

VDDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage.

Two voltage detection circuits are provided to monitor the external supply voltage (VDDD) for falling and rising

levels, each configurable for one of the 26 selectable levels.

All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic.

The BOD and OVD circuits on VDDA can be configured to generate either a reset, or a fault.

3.2.2

Regulators

CYT4BF contains three regulators that provide power to the low-voltage core transistors: DeepSleep, core

internal, and core external. These regulators accept a 2.7-V to 5.5-V VDDD supply and provide a low-noise 1.1-V

supply to various parts of the device. These regulators are automatically enabled and disabled by hardware and

firmware when switching between power modes. The core internal and core external regulators operate in Active

mode, and provide power to the CPU subsystem and associated peripherals.

3.2.2.1

DeepSleep

The DeepSleep regulator is used to maintain power in a small number of blocks when in DeepSleep mode.

These blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other

configuration memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal

regulator is disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is

disabled.

3.2.2.2

Core internal

The core internal regulator supports load currents up to 300 mA, and is operational during device start-up

(boot process), and in Active/Sleep modes.

3.2.2.3

Core external[5]

To support worst-case loading, with both M7 CPUs and the M0+ CPU at their maximum clock frequency and all

integrated peripherals operating, a core external regulator is required, capable of load currents up to 600 mA.

While the control and monitor circuits for the core external regulator are internal to CYT4BF, the power

regulating element (NPN pass transistor, PMIC, or LDO) is external. This reduces the overall power dissipation

within the CYT4BF package, while maintaining a well-regulated core supply.

Note

5. When CYT4BF is in Hibernate mode, the GPIO used to control the core external regulator are High-Z. This may require an external

pull-up or pull-down resistor to disable the external regulator and configure it for minimum operating current.

CYT4BFCCJS 데이터시트(PDF) 13 Page - Infineon Technologies AG

CYT4BFCCJS 데이터시트(HTML) 13 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL