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PT2000 데이터시트(PDF) 96 Page - NXP Semiconductors |
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PT2000 데이터시트(HTML) 96 Page - NXP Semiconductors |
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96 / 148 page ![]() NXP Semiconductors 96 PT2000 8.3.2.15 Microcore0 interrupt status register This 13-bit register stores the information about the interrupt currently being served by uc0. If no interrupt is being served, this register is cleared. • Interrupt_routine_in_progress: '1' when an interrupt is being served. • Irq_source: • “000”: serving start rising edge interrupt • “001”: serving driver disable interrupt request • “010”: serving automatic diagnostics interrupt request • “011”: serving start falling edge interrupt • “100”: serving software interrupt request 0 • “101”: serving software interrupt request 1 • “110”: serving software interrupt request 2 • “111”: serving software interrupt request 3 • Iret_address: the value of the return address after the interrupt is served. The return address after an interrupt is always the address where the code execution would continue if no interrupt had occurred. For wait and conditional jump instructions, the address is defined considering the status of the feedback at the moment the interrupt request took place. 8.3.2.16 Microcore1 interrupt status register This 13-bit register stores the information about the interrupt currently being served by uc1. If no interrupt is being served, this register is cleared. • Interrupt_routine_in_progress: '1' when an interrupt is being served. • Irq_source: • “000”: serving start rising edge interrupt • “001”: serving driver disable interrupt request • “010”: serving automatic diagnostics interrupt request • “011”: serving start falling edge interrupt • “100”: serving software interrupt request 0 • “101”: serving software interrupt request 1 • “110”: serving software interrupt request 2 • “111”: serving software interrupt request 3 • Iret_address: the value of the return address after the interrupt is served. Table 73. uc0_irq_status (10Fh, 12Fh, 14Fh) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved interrupt_ro utine_in_pro gress irq_source iret_address R/W - r r r Lock - no no no Reset 00 0 000 1111111111 Table 74. uc1_irq_status (110h, 130h, 150h) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Reserved interrupt_ro utine_in_pro gress irq_source iret_address R/W - r r r Lock - no no no Reset 00 0 000 1111111111 |
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