MPC7410EC datasheet(34/56 Pages) NXP

34 / 56 page

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

System Design Information

7.6 Substrate Capacitors for the MPC7410

Figure 20 shows the connectivity of the substrate capacitor pads for the MPC7410, 360 CBGA and 360 HCTE

packages.

Figure 20. Substrate Bypass Capacitors for the MPC7410

System Design Information

This section provides electrical and thermal design recommendations for successful application of the MPC7410.

8.1 PLL Configuration

The MPC7410 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL

configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the

MPC7410 is shown in Table 13 for example frequencies. In this example, shaded cells represent settings that, for a

given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the minimum and

maximum core frequencies listed in Table 8.

Table 13. MPC7410 Microprocessor PLL Configuration

PLL_CFG

[0:3]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Multiplier

Core-to

VCO

Multiplier

Bus

33.3 MHz

Bus

50 MHz

Bus

66.6 MHz

Bus

75 MHz

Bus

83.3 MHz

Bus

100 MHz

Bus

133 MHz

0100

—

0110

2.5x

—

1000

—

400

(800)

1110

3.5x

—

—350

(700)

465

(930)

1010

—

—400

(800)

—

Package

Caps

Value

µF

Voltage

Reference

C1-1

0.01

L2OVDD

C1-2

GND

C2-1

0.01

L2OVDD

C2-2

GND

C3-1

0.01

VDD

C3-2

GND

C4-1

0.01

OVDD

C4-2

GND

C5-1

0.01

OVDD

C5-2

GND

C6-1

0.01

VDD

C6-2

GND

A1 CORNER

C1-1

C1-2

C2-1

C2-2

C3-2

C3-1

C4-2

C4-1

C5-2

C5-1

C6-1

C6-2

MPC7410EC 데이터시트(PDF) 34 Page - NXP Semiconductors

MPC7410EC 데이터시트(HTML) 34 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

데이터시트 다운로드

링크 URL