PIC16F616-ESLASHML datasheet(101/172 Pages) APEX

101 / 172 page

Preliminary

DS41288A-page 99

PIC16F616/16HV616

11.2

Calibration Bits

The 8 MHz internal oscillator is factory calibrated.

These calibration values are stored in fuses located in

the Calibration Word (2009h). The Calibration Word is

not erased when using the specified bulk erase

sequence in the “PIC12F6XX/16F6XX Memory Pro-

gramming Specification” (DS41204) and thus, does not

require reprogramming.

11.3

Reset

The

PIC16F616/16HV616

differentiates

between

various kinds of Reset:

Power-on Reset (POR)

WDT Reset during normal operation

WDT Reset during Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

Brown-out Reset (BOR)

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset

•MCLR Reset

•MCLR Reset during Sleep

• WDT Reset

• Brown-out Reset (BOR)

WDT wake-up does not cause register resets in the

same manner as a WDT Reset since wake-up is

viewed as the resumption of normal operation. TO and

PD bits are set or cleared differently in different Reset

situations, as indicated in Table 11-2. Software can use

these bits to determine the nature of the Reset. See

Table 11-4 for a full description of Reset states of all

registers.

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 11-1.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 15.0 “Electrical

Specifications” for pulse-width specifications.

FIGURE 11-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/VPP pin

VDD

OSC1/

WDT

Module

VDD Rise

Detect

OST/PWRT

On-Chip

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

11-bit Ripple Counter

Reset

Enable OST

Enable PWRT

Sleep

Brown-out(1)

Reset

BOREN

CLKI pin

Note

Refer to the Configuration Word register (Register 11-1).

RC OSC

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