USB5742B

DS00002016H-page 36

10.6.3

RESET AND CONFIGURATION STRAP TIMING

Figure 10-4 illustrates the RESET_N pin timing requirements and its relation to the configuration strap pins. Assertion

of RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified. Refer to Sec-

tion 8.2, "Resets" for additional information on resets. Refer to Section 3.4, "Configuration Straps and Programmable

Functions" for additional information on configuration straps.

10.6.4

USB TIMING

All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Uni-

versal Serial Bus Specification

. Please refer to the Universal Serial Bus Revision 3.2 Specification, available at http://

www.usb.org/developers/docs.

10.6.5

uments/user_manual/UM10204.pdf.

10.6.6

SMBUS TIMING

All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Sys-

tem Management Bus Specification.

Please refer to the System Management Bus Specification, Version 1.0, available

at http://smbus.org/specs.

FIGURE 10-4:

RESET_N CONFIGURATION STRAP TIMING

TABLE 10-7:

RESET_N CONFIGURATION STRAP TIMING

Symbol

Description

Min

Typ

Max

Units

RESET_N input assertion time

5

s

Configuration strap pins hold after RESET_N deassertion

1

ms

Note:

The clock input must be stable prior to RESET_N deassertion.

Configuration strap latching and output drive timings shown assume that the Power-On reset has finished

first otherwise the timings in Section 10.6.2, "Power-On and Configuration Strap Timing" apply.

RESET_N

Configuration

Straps