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TMS320VC5441 데이터시트(PDF) 40 Page - Texas Instruments

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부품명 TMS320VC5441
상세설명  TMS320VC5441 Fixed-Point Digital Signal Processor
PDF  86 Pages
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TMS320VC5441 데이터시트(HTML) 40 Page - Texas Instruments

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Functional Overview
31
December 1999 – Revised April 2002
SPRS122E
•
In the second mode, with RMCME = 1 and XMCME = 1, the McBSPs have 128-channel selection
capability. Twelve registers (RCERCx–RCERHx and XCERCx–XCERHx) are used to enable the
128-channel selection. The subaddresses of the registers are shown in Table 3–24. These registers,
functionally equivalent to the RCERA0–RCERB1 and XCERA0–XCERB1 registers, are used to
enable/disable the transmit and receive of additional channel partitions (C,D,E,F,G, and H) in the
128-channel stream. For example, XCERH1 is the transmit enable for channel partition H (channels 112
to 127) of McBSP1 for each DSP subsystem. See Figure 3–18, Table 3–8, Figure 3–19, and Table 3–9
for bit layouts and functions of the receive and transmit registers.
15
14
13
12
11
10
9
8
RCERyz15
RCERyz14
RCERyz13
RCERyz12
RCERyz11
RCERyz10
RCERyz9
RCERyz8
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
76
54
32
10
RCERyz7
RCERyz6
RCERyz5
RCERy4
RCERyz3
RCERyz2
RCERyz1
RCERyz0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
LEGEND: R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2
Figure 3–18. Receive Channel Enable Registers Bit Layout for Partitions A to H
Table 3–8. Receive Channel Enable Registers for Partitions A to H
Bit
Name
Function
15–0
RCERyz[15:0]
Receive Channel Enable Register
RCERyz n =0
Disables reception of nth channel in partition y.
RCERyz n =1
Enables reception of nth channel in partition y.
Note:
y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15–0
15
14
13
12
11
10
9
8
XCERyz15
XCERyz14
XCERyz13
XCERyz12
XCERyz11
XCERyz10
XCERyz9
XCERyz8
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
76
54
32
10
XCERyz7
XCERyz6
XCERyz5
XCERy4
XCERyz3
XCERyz2
XCERyz1
XCERyz0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
RW,+0
LEGEND: R = Read, W = Write, +0 = Value at reset; y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2
Figure 3–19. Transmit Channel Enable Registers Bit Layout for Partitions A to H
Table 3–9. Transmit Channel Enable Registers for Partitions A to H
Bit
Name
Function
15–0
XCERyz[15:0]
Transmit Channel Enable Register
XCERyz n =0
Disables transmit of nth channel in partition y.
XCERyz n =1
Enables transmit of nth channel in partition y.
LEGEND: y = Partition A,B,C,D,E,F,G, or H; z = McBSP 0,1, or 2; n = bit 15–0



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