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capacitors are preferred.

Use as much VIAs as possible when power traces have to move between different planes on the PCB:

this reduces both parasitic resistance and inductance. Moreover, reproducing the same high-current trace

on more than one PCB layer will reduce the parasitic resistance associated to that connection.

Connect output bulk capacitor as near as possible to the load, minimizing parasitic inductance and resis-

tance associated to the copper trace also adding extra decoupling capacitors along the way to the load

when this results in being far from the bulk capacitor bank.

Figure 24. Power connections and related connections layout guidelines (same for all phases).

18.2 Power Connections Related.

Figure 24 shows some small signal components placement.

mosfet. The device robustness allows managing applications with the power section far from the

controller without losing performances. Anyway, when possible, it is suggested to minimize the distance

between controller and power section.

In addition, since the PHASEx pin is the return path for the high side driver, this pin might be connected

directly to the High Side mosfet Source pin to have a proper driving for this mosfet. For the LS mosfets,

the return path is the PGNDx pin: it can be connected directly to the power ground plane.

the loop that is created.

capacitor sustains the peak currents requested by the low-side mosfet drivers.

current delivered causes errors in the device behavior.

noise.

driving net for this pin in order to minimize coupled noise.

PHASEx pins. If these voltage spikes overcome the max breakdown voltage of the pin, the device can

L

UGATEx

PHASEx

LGATEx

PGNDx

LOAD

BOOTx

PHASEx

VCC

SGND

+Vcc

L

LOAD

To limit C

BOOT

Extra-Charge

a. PCB power and ground planes areas

b. PCB small signal components placement