VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

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OC-48 (FEC) 16:1 SONET/SDH

MUX with Clock Generator

G52230-0, Rev 3.6

Page 3

01/02/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Figure 2: Enabling FIFO Operation

Figure 3: Split-End DC Termination of CLK16O+/-, REFCLKO+/-

Figure 4: Traditional DC Termination of CLK16O+/-, REFCLKO+/-

Minimum 5 CLK16 cycles

FIFO Mode Operation

Transparent Mode Operation

Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation.

Holding RESET constantly “low” bypasses the FIFO for transparent mode operation.

PLL locked to reference clock.

RESET

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R2

R2

R1

R1

R1+R2

R1 = 125

Ω R2 = 83Ω, Zo=50Ω, V

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50

Ω

50

Ω