8 of 11

24149 - 1

38

39

43

42

19

22

NOTES: Resistors 1, 2, 3 and 4 are used to set the VCO centre frequency. For 143/177 Mb/s

≈ 6kΩ, 270 Mb/s ≈ 2.7kΩ, 360 Mb/s ≈ 1.8kΩ

All resistors in ohms, all capacitors in microfarads unless otherwise stated.

represent test points.

DATA

+10

20

26

6

2,5,21,28,40,41

+5V

18,23

25,27

30,37

44

17

36

35

29

0.1

*150

34

33

32

31

1,4

1

2

3

4

10k

DATA RATE

SELECT DIP

SWITCH

(SEE TRUTH TABLE,

FIG. 2)

5k

100

100

6x100n

82

2N4400

+5V

LOOP

LOCKED

L.E.D.

PARALLEL

CLOCK OUT

330

DATA 0

DATA 1

DATA 2

DATA 3

DATA 4

DATA 5

DATA 6

DATA 7

DATA 8

DATA 9

CLOCK

3.9k

0.1

0.1

GS9002A

PD0

PDI

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PD9

PCK IN

DRS0

DRS1

CREG

RVCO1 RVCO2 RVCO3 RVCO4 VEE

LOCK

SSS

SYNC (6x VCC)

DET.

DIS.

SCK

PCK-OUT

LOOP FILT

10k

4x0.1

820

COMMON

+5V

10k

1k

8

9

10

11

12

13

14

15

16

100

DATA

CLOCK

CLOCK

100

SDO

SDO

SCK

7

+5V

1M

*10p

Fig. 11 GS9002A Test Circuit

Fig. 10 Timing Diagram

E

A

V

S

A

V

4ƒsc

DATA

STREAM

ACTIVE VIDEO

& H BLANKING

T

R

S

SYNC

DETECT

ACTIVE

VIDEO

T

R

S

T

R

S

ACTIVE VIDEO

& H BLANKING

4:2:2

DATA

STREAM

PCLK IN

PDN

SYNC

DETECT

E

A

V

S

A

V

H

BLNK

H

BLNK

SYNC

DETECT

XXX 3FF

000

000

XXX

•••

•••

XXX

3FF

000

000

XXX

•••