UCC28C53_V01 datasheet(14/48 Pages) TI

14 / 48 page

8.2 Functional Block Diagram

VREF

VREF Good

Logic

UVLO

Osc

PWM

Latch

1 V

E/A

VDD

RT/CT

COMP

PWM

Comparator

VREF

OUT

GND

2. 5 V

( NOTE)

5 V

Toggle flip-flop used only in UCCx8C51, UCCx8C54, UCCx8C55, UCC28C57H/L, and UCC28C59

8.3 Feature Description

The BiCMOS design allows operation at high frequencies that were not feasible in the predecessor bipolar

devices. First, the output stage has been redesigned to drive the external power switch in approximately half

the time of the earlier devices. Second, the internal oscillator is more robust, with less variation as frequency

increases. This faster oscillator makes this device suitable for high speed applications and the trimmed

discharge current enables precise programming of the maximum duty cycle and dead-time limit. In addition,

the current sense to output delay is kept the same 45 ns (typical) as UCCx8C4x. Such a delay time in the

current sense results in superior overload protection at the power switch. The reduced start-up current of this

device minimizes steady state power dissipation in the startup resistor, and the low operating current maximizes

efficiency while running, increasing the total circuit efficiency, whether operating off-line, DC input, or battery

operated circuits. These features combine to provide a device capable of reliable, high-frequency operation.

Table 8-1. Improved Key Parameters

PARAMETER

UCCx8C4x

UCCx8C5x

Supply current at 52 kHz

2.3 mA

1.3 mA

Start-up current, maximum

100 µA

75 µA

VVDD absolute maximum

20 V

30 V

Reference voltage accuracy

± 1%

UVLO and Dmax for Si FETs

6 options

UVLO and Dmax for SiC FETs

No options

6 options

Smallest package option

VSSOP (8)

UCC28C53, UCC28C54, UCC28C55

UCC28C56H, UCC28C57H, UCC28C57L, UCC28C59

SLUSER8 – JUNE 2022

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