Symbol

Alt

Parameter

Min

Max

Unit

Clock Rise Time

1

µs

Clock Fall Time

300

ns

Input Rise Time

1

µs

Input Fall Time

300

ns

(1)

Clock High to Input Transition

4.7

µs

Clock Pulse Width High

4

µs

Input Low to Clock Low (START)

4

µs

Clock Low to Input Transition

0

µs

Clock Pulse Width Low

4.7

µs

Input Transition to Clock Transition

250

ns

Clock High to Input High (STOP)

4.7

µs

Input High to Input Low (Bus Free)

4.7

µs

(2)

Clock Low to Next Data Out Valid

0.3

3.5

µs

Data Out Hold Time

300

ns

Clock Frequency

100

kHz

(3)

Write Time

10

ms

Notes: 1. For a reSTART condition, or following a write cycle.

2. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP

conditions.

3. In the Multibyte Write mode only, if accessed bytes are on two consecutive 8 bytes rows (6 address MSB are not constant) the

maximum programming time is doubled to 20ms.

Table 7. AC Characteristics

The 4 most significant bits of the device select code

are the device type identifier, corresponding to the

are fixed as 1010b. The following 3 bits identify the

specific memory on the bus. They are matched to

the chip enable signals E2, E1, E0. Thus up to 8 x

2K memories can be connected on the same bus

giving a memory capacity total of 16K bits. After a

START condition any memory on the bus will iden-

tify the device code and compare the following 3

bits to its chip enable inputs E2, E1, E0.

The 8th bit sent is the read or write bit (RW), this

bit is set to ’1’ for read and ’0’ for write operations.

If a match is found, the corresponding memory will

acknowledge the identification on the SDA bus

during the 9th bit time.

Input Rise and Fall Times

≤ 50ns

Input Pulse Voltages

AC MEASUREMENT CONDITIONS

AI00825

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Figure 4. AC Testing Input Output Waveforms

DEVICE OPERATION (cont’d)

6/16

ST24/25C02, ST24C02R, ST24/25W02