MPFS025T datasheet(31/50 Pages) MICROCHIP

31 / 50 page

Figure 4-4. I/O Topology

pad

I/O

Lane

Control

I/O Gearing

IOP

ION

I/O Gearing

IOP

ION

I/O Gearing

IOP

ION

I/O Gearing

IOP

ION

I/O Gearing

IOP

ION

I/O Gearing

IOP

ION

The number of I/O pins varies depending on the device and package size. The persistent I/O feature preserves a

state on an I/O without user intervention during programming. The PolarFire SoC FPGA I/O buffers are constructed

from the following main sub modules.

• Transmit buffer (PVT compensated)

• Receive buffer

• Termination (Thevenin, Differential, Up, and Down)

• Weak pull mode logic (Up, Down, and Bus-Hold)

Each I/O is configurable and can comply with a large number of I/O standards. The following are two types of user

FPGA I/Os in PolarFire SoC FPGAs.

• High-speed I/O (HSIO) optimized for DDR4 memories at speeds up to 1.6 Gbps and a maximum voltage of 1.8

V nominal

• GPIO capable of supporting multiple standards including 3.3 V with an integrated CDR to support SGMII

Ethernet applications

The following table summarizes the single-ended I/O support. These are the unterminated standards used in the

transceiver lane protocols. Each I/O supports weak pull-up, pull-down, and bus-keeper options. Additionally, each

GPIO has a programmable clamp (that is, ON/OFF). For HSIO, the clamp is always ON.

The following table lists the GPIO LVTTL or LVCMOS receivers that are also designed to support a limited mixed

mode of operation to provide greater board I/O design flexibility. For example, if VDDIO is set to 3.3 V, the I/O

receivers can operate at the lower voltage of JEDEC standards.

Table 4-2. GPIO Mixed Receiver Mode Operation Capability

VDDIO (V)

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

LVCMOS12

3.3

Yes

Not available

Yes

2.5

Yes

1.8

Yes

1.5

Yes

1.2

Yes

Not available

Yes

The following table lists the HSIO mixed receiver mode capability.

Table 4-3. HSIO Mixed Receiver Mode Capability

VDDIO (V)

LVCMOS18

LVCMOS15

LVCMOS12

1.8

Yes

1.5

Yes

Programmable Logic Subsystem

and its subsidiaries

Overview

DS60001656C-page 31

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