MPFS160T datasheet(3/50 Pages) MICROCHIP

3 / 50 page

• 1.0 V and 1.05 V operating modes

Low-Power Features

• Low device static power

• Low inrush current

• Low-power transceivers

Reliability Features

• FPGA configuration cells single-event upset (SEU) immune

• Built-in SECDED and memory interleaving on FPGA fabric LSRAMs

• SECDED on all processor memories

– Error signals trapped and exported to the FPGA fabric

• System controller suspend mode for safety-critical designs

Security Features

• Cryptography Research Incorporated (CRI)-patented differential power analysis (DPA) bitstream protection

• Integrated dual physically unclonable function (PUF)

• 56 KB of secure, non-volatile memory (sNVM)

• Built-in tamper detectors and countermeasures

• Digest integrity check for FPGA, µPROM, sNVM, and eNVM

• Side channel resistant Crypto co-processor in "S" data security devices

SoftConsole Embedded IDE

• Eclipse IDE

• Firmware catalog for device drivers

Libero® SoC Design Suite

• Complete FPGA development environment

• Includes Synplify Pro synthesis and Mentor ModelSim ME simulation

PolarFire SoC MSS Configurator

• Generates a Libero MSS component for the FPGA design

• Generates C data structures to initialize the memory map in the embedded environment

• Configures the following:

– MSS clocks

– Fabric interfaces

– IO banks

– DDR memories

– Debug features

PolarFire SoC Icicle Kit

The Icicle kit is a low-cost development platform for the PolarFire SoC FPGA. It features:

• PolarFire SoC FPGA (MPFS250T-FCVG484E)

• 2 GB LPDDR4 memory

• 8 GB eMMC

• SD card interface

• 4 x 12.7 Gbps SERDES

and its subsidiaries

Overview

DS60001656C-page 3

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