STM32F407IE datasheet(105/201 Pages) STMICROELECTRONICS

105 / 201 page

DocID022152 Rev 6

105/201

STM32F405xx, STM32F407xx

Electrical characteristics

5.3.11

PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic

interferences (see Table 44: EMI characteristics). It is available only on the main PLL.

Equation 1

The frequency modulation period (MODEPER) is given by the equation below:

fPLL_IN and fMod must be expressed in Hz.

As an example:

If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by

equation 1:

Equation 2

Equation 2 allows to calculate the increment step (INCSTEP):

fVCO_OUT must be expressed in MHz.

IDD(PLLI2S)(4)

PLLI2S power consumption on

VDD

VCO freq = 100 MHz

VCO freq = 432 MHz

0.15

0.45

0.40

0.75

IDDA(PLLI2S)(4)

PLLI2S power consumption on

VDDA

VCO freq = 100 MHz

VCO freq = 432 MHz

0.30

0.55

0.40

0.85

1. Take care of using the appropriate division factor M to have the specified PLL input clock values.

2. Guaranteed by design.

3. Value given with main PLL running.

4. Guaranteed by characterization.

Table 37. PLLI2S (audio PLL) characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 38. SSCG parameters constraint

Symbol

Parameter

Min

Typ

Max(1)

Unit

fMod

Modulation frequency

KHz

Peak modulation depth

0.25

MODEPER * INCSTEP

215

−1-

1. Guaranteed by design.

MODEPER

round fPLL_IN

4fMod

()

⁄

[]

MODEPER

round 10

410

()

⁄

[]

250

INCSTEP

round

–

() md PLLN

()

100

MODEPER

()

⁄

[]

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