CC2430-RTR1-F64Z datasheet(130/234 Pages) TI

130 / 234 page

CC2430

CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A

Page 130 of 232

ADCH (0xBB) – ADC Data High

Bit

Name

Reset

R/W

Description

7:0

ADC[13:6]

0x00

Most significant part of ADC conversion result.

ADCCON1 (0xB4) – ADC Control 1

Bit

Name

Reset

R/W

Description

EOC

End of conversion Cleared when both ADCH and ADCL has been

read. If a new conversion is completed before the previous data

has been read, the EOC bit will remain high.

conversion not complete

conversion completed

R/W1

Start conversion. Read as 1 until conversion has completed

no conversion in progress

start a conversion sequence if ADCCON1.STSEL = “11” and

no sequence is running.

5:4

STSEL[1:0]

R/W

Start select. Selects which event that will start a new conversion

sequence.

External trigger on P2_0 pin.

Full speed. Do not wait for triggers.

Timer 1 channel 0 compare event

ADCCON1.ST = 1

3:2

RCTRL[1:0]

R/W

Controls the 16 bit random number generator. When written 01,

the setting will automatically return to 00 when operation has

completed.

Normal operation. (13x unrolling)

Clock the LFSR once (no unrolling).

Reserved

Stopped. Random number generator is turned off.

1:0

R/W

Reserved. Always set to 11.

CC2430-RTR1-F64Z 데이터시트(PDF) 130 Page - Texas Instruments

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