2

ICS95V847

0718D—04/08/05

Pin Descriptions

ICS95V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential

pair of clock outputs (CLKT[4:0], CLKC[4:0]) and one differential pair feedback clock output (FB_OUT, FB_OUTC).The

clock outputs are controlled by input clock (CLK_INT, CLK_INC), the feedback clock (FB_INT, FB_INC) and the analog

The PLL in ICS95V847 clock driver uses the input clock (CLK_INC, CLK_INT) and the feedback clock (FB_INT,

FB_INC) to provide high-performance, low-skew, low-jitter differential output clocks (CLKT[4:0], CLKC[4:0]). ICS95V847

is also able to track Spread Spectrum Clock (SSC) for reduced EMI.

ICS95V847 is characterized for operation from 0°C to 85°C.

R

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B

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