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LEOLVDSRDPT-D 데이터시트(PDF) 7 Page - STMicroelectronics

부품명 LEOLVDSRDPT-D
상세설명  Rad-hard plastic LVDS driver-receiver
PDF  23 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LEOLVDSRDPT-D 데이터시트(HTML) 7 Page - STMicroelectronics

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Symbol
Parameters
Test conditions
Min.
Typ.
Max.
Unit
TPLHD
Load: refer to Figure 4. Test circuit,
timing and voltage definitions for
differential output signal for the driver
Propagation delay time, low to
high output
0.5
1.5
Tr
Differential output signal rise
time
0.8
Tf
Differential output signal fall
time
0.8
TSK
Chip-to-chip skew(1) (2)
0.7
ns
TSKD
Differential skew (TPHLD-
TPLHD)(3)
0.3
TPHZ
Propagation delay time, high
level to high impedance output
Load: refer to Figure 5. Enable and
disable waveforms for the driver
2.8
TPLZ
Propagation delay time, low
level to high impedance output
2.8
TPZH
Propagation delay time, high
impedance to high level output
2.5
TPZL
Propagation delay time, high
impedance to low level output
2.5
Receiver
VTL
Differential input low threshold
VCM = 1.2 V
-100
mV
-4 V < VCM < +4 V
-130
VTH
Differential input high
threshold
VCM = 1.2 V
+100
-4 V < VCM < +4 V
+130
VCL
LVCMOS input clamp voltage
ICL = 18 mA
1.5
V
VCMREJ
Common mode rejection(2)
F = 10 MHz
300
mVpp
IID
Differential input current
VID = 400 mVp-p
-10
+10
µA
IICM
Common mode input current
VCM = - 4 V to + 4 V
-70
+70
µA
VOH
Output voltage high
IOH = -0.4 mA, VCC = 3 V
2.7
V
VOL
Output voltage low
IOL = 2 mA, VCC = 3 V
0.25
V
IOS
Output short-circuit current
VOUT = 0 V
-90
-30
mA
IOZ
Output tri-state current
Disabled, VOUT = 0 V or VCC
-10
+10
µA
CIN
Input capacitance
IN+ or IN- to GND
3
pF
ROUT
Output resistance
45
ohm
TPHLD
Propagation delay time, high-
to-low output
VID = 200 mVp-p, input pulse
from 1.1 V to 1.3 V, VCM = 1.2 V
Load: refer to Figure 6. Timing test
circuit and waveforms for the receiver
1
2.5
ns
TPLHD
Propagation delay time, low-
to-high output
1
2.5
Tr
Output signal rise time
Load: refer to Figure 6. Timing test
circuit and waveforms for the receiver
0.9
ns
Tf
Output signal fall time
0.9
TSK
Chip-to-chip skew(1),(2)
0.7
TSKD
Differential skew (TPHLD-
TPLHD)
(3)
0.3
TPHZ
Propagation delay time, high
level to high impedance output
Load: refer to Figure 7. Enable and
disable waveforms for the receiver
3.8
ns
TPLZ
Propagation delay time, low
level to high impedance output
3.8
LEOLVDSRD
Electrical characteristics
DS13673 - Rev 4
page 7/23



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