RHRDAC1612 datasheet(21/47 Pages) STMICROELECTRONICS

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RHRDAC1612

DAC operation

DocID029369 Rev 2

21/47

Standy = standy mode of DAC

Operating = normal operation of DAC.

10. CAL = flag that indicates the start/end of the calibration

11. Offset change = function that changes the offset register value

12. Calibration = function that calibrates the offset error. When the function starts, CAL = 0

and when the function ends, CAL = 1.

4.7

ARSTN and PDN digital pin functions

ARSTN

ARSTN is an input that allows the RHRDAC1612 to be reset asynchronously. This input is

active at low level (“0” logic) and has total priority vs. the PDN input and SPI control.

While ARSTN = “0” logic, the registers of the RHRDAC1612 cannot be set. A read of these

registers gives 00h.

When ARSTN changes from “0” to “1” logic, all values in the register are set to default as

indicated in Table 6 (see POR or ARSTN column).

PDN

PDN is an input that allows the RHRDAC1612 to be set asynchronously in standby. This

input is active at low level (“0” logic). Despite the standby feature, this input must be used

to set/reset the bits Vseries and RC EN at address 01h as shown in Figure 17: "DAC

operation flow chart (continued)".

Table 6 below shows the truth table of ARSTN and PDN.

Table 7: Truth table of ARSTN and PDN

ARSTN

PDN

Icc

Vout

Standby

HiZ state

≈ 2.2 mA

LowZ, equal to ≈ VREFIN (it is not recommended to use this

combination)

Operating

LowZ operating, Vout = f (code in Adr 02h)

4.8

Power-on-reset (POR) feature

The RHRDAC1612 integrates an internal POR connected to AVCC. POR levels are given

in Table 13: "Electrical characteristics". If AVCC does not reach 2 V to 2.3 V when AVCC

increases, the internal POR forces a reset equivalent to ARSTN = 0. If AVCC does not

reach 2 V to 1.7 V when AVCC decreases, the internal POR is not active.

4.9

Power supply sequencing

The RHRDAC1612 has three different power supplies (AVCC, DVCC, and IOVCC). These

power supplies must be set and reset as described in Figure 23: "DAC timing diagram 2"

and the amplitude must respect values in Table 12: "Operating conditions (Tamb from -55

°C to 125 °C)".

To avoid unwanted behavior on the output during power supply sequencing, it is also

advised to keep the ARSTN and PDN inputs at low levels (GND).

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