L6364 datasheet(28/60 Pages) STMICROELECTRONICS

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The data is sent by using push-pull operation of the output switches. Writing either the LINK:SND or LINK:END

bit clears the STATUS:DAT and STATUS:CHK status flags. The data output is synchronized using the internal PLL

clock.

As defined in the IO-Link specification v1.1, the device has a maximum of 10xTBIT periods to process the

incoming message and prepare the response. A delay of up to TBIT/16 can be incurred in the L6364 due to

synchronization with the internal PLL clock, leaving the microcontroller slightly less than 10xTBIT to respond.

9.6

Clock recovery

The L6364 has an internal RC clock with a nominal frequency of fCK. The filtered data line is monitored for

transitions while in the IOListen and SIOListen states.

When a first rising edge is seen, the internal PLL clock phase is aligned to the incoming data. The PLL clock

corrects its operational frequency on the detection of further rising edges.

See Section 8.2.7 regarding detailed operation in single octet mode. The clock correction has a resolution of

0.4%(TYP) and a stability of 1%(MAX) over the duration of a message.

L6364

Clock recovery

DS13363 - Rev 4

page 28/60

L6364 데이터시트(PDF) 28 Page - STMicroelectronics