L9396 datasheet(69/109 Pages) STMICROELECTRONICS

69 / 109 page

DS12539 Rev 6

69/109

L9396

System functional safety implementations

108

Figure 12. Reset output logic diagram

-40°C ≤ Tj ≤ 175 °C; 3 V ≤ VCC ≤ 5.5 V, 5.6 ≤ VBST ≤ 19 V unless otherwise specified.

7.2.4

Oscillator

The IC implements a clock frequency validation circuit. CLK ERR flag is the error signal

reporting a problem with the integrated oscillator source. If the frequency of the integrated

oscillator moves away from the desired one, the error flag is set. The check is performed by

comparing the main oscillator with a secondary one; in case the frequency of the main

oscillator shifts out of the specified range (in case of a stuck oscillator the CLOCK TIMEOUT

ERROR is activated), the secondary oscillator source will recognize it, asserting the CLK

ERROR flag.

The Clock monitor check is performed also comparing the second oscillator to the first one.

The CLK ERROR flag is asserted also in case the frequency of the second oscillator shifts

out of the specified range. To reduce the emissions of the main logic core and of the

switching circuits in general, spread spectrum is operating on the main oscillator: the central

16 MHz frequency is varied by a triangular modulation at 125 kHz. Spread spectrum is

always active and can be disabled setting the SPREAD SPECTRUM DISABLE MODE bit in

the POWER_ON register.

GADG2401171135PS

CLKFRERR

VBG_READY

GNDA_ERR

VREG_ERR

WD2 RESET state

WD1 RESET state

VCORE_ERR

VCCx_ERR

RESET (pin)

WSM_Reset

SSM_Reset

POR

stretch

0.5ms

Table 49. Reset electrical characteristics

Symbol

Parameter

Conditions/Comments

Min.

Typ.

Max.

Unit

VOL

RESET Logic Output

Low Voltage

5 kΩ tied to VCC

0.4

VOH

RESET Logic Output

High Voltage

5 kΩ tied to VCC

VCC-

0.05

Rise time

Load = 50 pF; 20%-80%

µs

Fall time

Load = 50 pF; 20%-80%

µs

Ileak_RESET RESET leakage current

RESET output off

0<RESET<VCC

-2

µA

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