L9177 datasheet(13/49 Pages) STMICROELECTRONICS

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L9177

Electrical specifications

3.5.2

Key

Figure 3. Input threshold

Figure 4. Key block diagram

VB UVL

Undervoltage disable LOW

threshold

3.5

3.7

3.9

VB UVh

Undervoltage threshold

hysteresis

0.3

IVB(dis)

Standby current

VB= 13 V, device

disabled, KEY<0.7 V

120

μA

IVB

Quiescent current

VB= 13 V, outputs

floating

Vrext

ASIC Bias reference

Application note

1.22

fint_clk

Internal clock reference

Application note

5.6

MHz

Table 7. Supply electrical characteristics (continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

Table 8. Key electrical characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Unit

V_Key_L

Input low threshold

1.5

V_Key_H

Input high threshold

3.3

V_Key_Hyst

Input voltage hysteresis

0.5

1.8

R_Key

Internal pull down

150

300



T_key_deglitch Key input filter time

Guaranteed by scan

μs

T_key_delay

Maximum delay time from

Key to regulator enable

Time from key rising

edge to 20% VDD

rising edge

200

μs

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