CS47L63 datasheet(40/300 Pages) CIRRUS

40 / 300 page

DS1085F3

CS47L35

4.3 Digital Core

The CS47L35 supports multiple signal paths through the digital core. Stereo full-duplex sample-rate conversion is provided

to allow digital audio to be routed between input (ADC) paths, output (DAC) paths, Digital Audio Interfaces (AIF1–AIF3)

and SLIMbus paths operating at different sample rates.

The DSP functions are highly programmable, using application-specific control sequences. Note that the DSP

configuration data is lost whenever the DCVDD power domain is removed; the DSP configuration data must be

downloaded to the CS47L35 each time the device is powered up.

The procedure for configuring the CS47L35 DSP functions is tailored to each customer’s application; please contact your

Cirrus Logic representative for more details.

The digital core incorporates a S/PDIF transmitter that can provide a stereo S/PDIF output on a GPIO pin. Standard

sample rates of 32–192 kHz can be supported. The CS47L35 incorporates a tone generator that can be used for beep

functions through any of the audio signal paths. A white-noise generator is incorporated, to provide comfort noise in cases

where silence (digital mute) is not desirable.

A haptic signal generator is provided, for use with external haptic devices (e.g., mechanical vibration actuators). Two

pulse-width modulation (PWM) signal generators are also provided; the PWM waveforms can be modulated by an audio

source within the digital core, and can be output on a GPIO pin.

An overview of the digital-core mixing and signal-processing functions is provided in Fig. 4-11.

The control registers associated with the digital-core signal paths are shown in Fig. 4-12 through Fig. 4-27. The full list of

digital mixer control registers (R1600–R2936) is provided in Section 6. Generic register field definitions are provided in

Table 4-7.

CS47L63 데이터시트(PDF) 40 Page - Cirrus Logic