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HVLED007TR 데이터시트(PDF) 21 Page - STMicroelectronics

부품명 HVLED007TR
상세설명  Transition mode PFC controller for flyback converters
PDF  33 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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HVLED007TR 데이터시트(HTML) 21 Page - STMicroelectronics

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DS12866 Rev 1
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HVLED007
Application information
33
and the programmed peak current is actually:
Equation 13
which can be derived from equations #3 and #4 in Table 7. As previously mentioned, if Ct is
selected with the criterion proposed in "Section 4.4: Shaping capacitor (Ct) selection (pin
CT)", this peak is no more than 5% lower than the value provided by equation #1 in Table 8.
The control loop easily compensates for that generating a Vcsref (θ) only slightly larger than
that predicted by equation # 3 in Table 7 by positioning the control voltage VCOMP at a level
slightly higher than that predicted by equation #1 in Table 7. However there is one more
point to be considered and that can be clarified with the aid of Figure 9:
 Case a) is that of normal operation just mentioned, i.e. with Vcsref (θ) more than ΔVcsref
(θ) / 2 away from Vcsmax so that the current sense signal is entirely in its linear operation
range.
 Case b) occurs when Vcsref (θ) is less than ΔVcsref (θ) / 2 away from Vcsmax; the peaks
of the ripple (Vcsref (θ) + ΔVcsref (θ) / 2) is clamped at Vcsmax. This impacts indirectly on
the envelope of the valleys Vcsref (θ) - ΔVcsref (θ) / 2 and, then, on Ippk (θ). In fact, as the
peaks of the ripple start being clamped, the smoothing resistor Rf has a loading effect on
the ICS circuit: the current flowing through Rf to the clamp is stolen from that charging Ct
so that the slope of the ascending ramps gets lower, whereas the descending ramps get
steeper. This alters the operation of the ICS circuit and results in a Vcsref (θ) and an
envelope of the valleys that are slightly flattened around the top of the sinusoid. In turn,
this flattens the peak of the input current sinusoid, increasing the THD.
 Case c) occurs when the peaks of the ripple (Vcsref (θ) + ΔVcsref (θ) / 2) not only exceed
Vcsmax with all the consequences discussed in the previous case but also the level
VCT_OL, which trips the overload protection (see "Section 4.9: Overload and short-circuit
protection (OCP function)"). This should be the case of a real overload but note that this
may occur - normally at low input voltage - even before Vcsref (θ) is clamped at Vcsmax
when ΔVcsref (θ) is too large (too small Ct and/or too large Rs). This is not the case if Ct
is selected with the criterion proposed in "Section 4.4: Shaping capacitor (Ct) selection
(pin CT)": ΔVcsref (θ) / 2 does not exceed 0.05·1.4 = 70 mV, while the difference VCT_OL
- Vcsmax is always greater than 100 mV.
Therefore, as a conclusion, for a given Ct (again, selected as per proposed criterion), if the
additional distortion caused at low line by the peaks of the ripple being clamped is
acceptable one can consider using the full dynamics of the current sense or nearly so, so
that the value of Rs is found from:
Equation 14
If the additional distortion is to be prevented, the full dynamics needs to be reduced
accordingly; then:
Ip pk
 = 4
Pin
V R
------- sin
1+Kv sin
Kv
--------------------------- 1
1
2Rt Ct
----------------
4Lp Pin
Kv VR
2
-------------------- sin



Rs
Vcsmax_min
Ip pk_max
-------------------------- =
1.2
Ip pk_max
----------------------



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