A121 Pulsed Coherent Radar (PCR)

Preliminary Datasheet v0.3

© 2022 Copyright by Acconeer

2022-09-22

Page 12 of 24

5

Timing Requirements

5.1 Serial Peripheral Interface

The Serial Peripheral Interface (SPI) is a 4-wire serial bus, used for configuration and reading output

from the A121 radar sensor. The A121 radar sensor is an SPI slave device connected to the SPI

master, as described in Figure 5.1. The A121 allows several devices to be connected on the same SPI

bus, with a dedicated slave-select signal. Daisy-chain is not supported.

Host

(SPI Master)

A121

(SPI Slave)

A121

(SPI Slave)

SPI_CLK

SPI_MOSI

SPI_SS1

SPI_SS2

SPI_MISO

Figure 5.1. SPI master-slave connection.

The serial data transfer input (MOSI) and output (MISO) to the A121 are synchronized by the

SPI_CLK. The Slave Select signal (SS) must be low before and during transactions. The MOSI is

always read on the rising edge of SCLK and the MISO changes value on the falling edge of SPI_CLK

(SPI mode 0, CPOL/CPHA = 0). SS requires release in between transactions. See Figure 5.2 and Table

5.1 for timing characteristics.

SPI_ClK

MOSI

MISO

SS

SS setup time

MSB

MOSI hold time

MOSI setup time

MISO propagation delay

SS hold time

LSB

15

15

14

14

13

13

0

0

1

1

2

2

Figure 5.2. Timing diagram of SPI, CPOL=0 and CPHA=0.