Functional Description

The MM5481 uses the MM5450 die which is packaged to

operate 2-digit alphanumeric displays with minimal interfer-

ence to the display and the data source Serial data transfer

from the data source to the display driver is accomplished

with 2 signals serial data and clock Using a format of a

leading ‘‘1’’ followed by the 35 data bits allows data transfer

without an additional load signal The 35 data bits are

latched after the 36th bit is complete thus providing non-

multiplexed direct drive to the display Outputs change only

if the serial data bits differ from the previous time Display

brightness is determined by control of the output current for

LED displays A 0001 mF capacitor should be connected to

brightness control pin 9 to prevent possible oscillations

A block diagram is shown in

Figure 1 The output current is

typically 20 times greater than the current into pin 9 which

is set by an external variable resistor There is an internal

limiting resistor of 400X nominal value

Figure 4 shows the input data format A start bit of logical

‘‘1’’ precedes the 35 bits of data At the positive-going-edge

of the 36th clock a LOAD signal is generated synchronously

with the high state of the clock which loads the 35 bits of

the shift registers into the latches At the low state of the

clock a RESET signal is generated which clears all the shift

registers for the next set of data The shift registers are a

static master-slave configuration There is no clear for the

master portion of the first shift register thus allowing conti-

nous operation

There must be a complete set of 36 clocks (highlow edges)

or the shift registers will not clear

Data Enable

This active low signal enables the data input pin If high the

shift register sees zeroes clocked in

To blank the display at any time (ie power on) clock in 36

or more zeroes followed by a ‘one’ (start bit) followed by

36 or more zeroes

Figure 5 shows the Output Data Format for the MM5481

Because it uses only 14 of the possible 34 outputs 20 of the

bits are ‘Don’t Cares’ Note that only alternate groups of 4

outputs are used

Figure 3 shows the timing relationships between data

clock and data enable A maximum clock frequency of

05 MHz is assumed

For applications where a lesser number of outputs are used

it is possible to either increase the current per output or

equation can be used for calculations

where

TLF6139 – 3

FIGURE 3 Timing

TLF6139 – 4

FIGURE 4 Input Data Format

3