ES9218PC datasheet(14/101 Pages) ESS

14 / 101 page

ES9218P Datasheet

December 6, 2018

CONFIDENTIAL ADVANCE INFORMATION 1.8

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

Volume Control

Each output channel has its own attenuation circuit. The attenuation for each channel is controlled independently. Each channel can be attenuated

from 0dB to –127dB in 0.5dB steps. Each 0.5dB step transition takes up to 64 intermediate levels, depending on the vol_rate setting in Register 6:

DoP and Volume Ramp Rate (0x06). The result being that the level changes are done using small enough steps so that no switching noise occurs

during the transition of the volume control. When a new volume level is set, the attenuation circuit will ramp softly to the new level.

The volume control can be either channel independent or synchronized using Register 27: General Configuration (0x1B) ch1_volume.

Master Trim

The master trim sets the 0dB reference level for the digital volume control of each DAC. The master trim is programmable via Register 17-20:

Master Trim (0x11 - 0x14). The master trim registers store a 32bit signed number.

This register value should never exceed the full scale signed value 32’h7FFFFFFF

Example: Setting the reference value to -1dB (from full-scale) = 32’h721482BF

System Clock XI(MCLK)

A system clock is required for proper operation of the digital filters and modulation circuitry.

Automatic clock gearing is supported to save power with the full XI(MCLK) clock rate is not required.

CLK =

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The minimum XI(MCLK) frequency must satisfy the following conditions:

Data Clock

DATA_CLOCK must be (2 x i2s_length) x FSR for PCM mode, and FSR for DSD modes. This pin should be pulled low if not used.

Built-in Digital Filters

Eight digital filters are included for PCM mode.

See PCM Filter Frequency Response for filter characteristics and Register 7: Filter Bandwidth and System Mute (0x07) for available filter settings.

Data Type

Minimum MCLK Frequency

DSD Data

CLK > 3 x FSR , FSR = 2.8224MHz (x 1, 2, or 4)

Serial Normal Mode

CLK > 128 x FSR, FSR

 384kHz

CLK = 128 x FSR (synchronous MCLK) with FSR

 384kHz

Serial OSF Bypass Mode

CLK > 24 x FSR, FSR

 768kHz

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