PC33975AR2 datasheet(14/32 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33975

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

POWER SUPPLY

The 33975 is designed to operate from 5.5 V to 38/40 V on

the VPWR terminal. Characteristics are provided from 8.0 V

to 28 V for the device. Switch contact currents and the

internal logic supply are generated from the VPWR terminal.

The VDD supply terminal is used to set the SPI

communication voltage levels, current source for the SO

driver, and pull-up current on INT and CS.

VDD supply may be removed from the device to reduce

quiescent current. If VDD is removed while the device is in

Normal mode, the device will remain in Normal mode. If VDD

is removed in Sleep mode, the device will remain in Sleep

mode until wake-up input is received (WAKE high to low,

switch input or interrupt timer expires).

Removing VDD from the device disables SPI

communication and will not allow the device to wake up from

INT

and CS terminals.

POWER-ON RESET (POR)

Applying VPWR to the device will cause a Power-ON

Reset and place the device in Normal mode.

Default settings from Power-ON Reset via VPWR or Reset

Command are as follows:

• Programmable Switch – Set to Switch-to-Battery

• All Inputs Set as Wake-Up

• Wetting Current On (16 mA pull down, 32 mA pull up)

• Wetting Current Timer On (20 ms)

• All Inputs Tri-State

• Analog Select 00000 (No Input Channel Selected)

Note The 33975 device provides indication that a reset

has occurred by placing a logic [1] in bit 22 of the SO buffer.

The reset bit is cleared on rising edge of CS.

OPERATIONAL MODES

The 33975 has two operating modes, Normal mode and

Sleep mode. A discussion on Normal mode begins below.

A discussion on Sleep Mode begins on page 20.

NORMAL MODE

Normal mode may be entered by the following events:

• Application of VPWR to the IC

• Change-of-Switch State (when enabled)

• Falling Edge of WAKE

• Falling Edge of INT (with VDD = 5.0 V and WAKE at

Logic [1])

• Falling Edge of CS (with VDD = 5.0 V)

• Interrupt Timer Expires

Only in Normal mode with VDD applied can the registers

of the 33975 be programmed through the SPI.

The registers that may be programmed in Normal mode

are listed below. Further explanation of each register is

provided in subsequent paragraphs.

• Programmable Switch Register (Settings Command)

• Wake-Up/Interrupt Register (Wake-Up/Interrupt

Command)

• Wetting Current Register (Metallic Command)

• Wetting Current Timer Register (Wetting Current Timer

Enable Command)

• Tri-State Register (Tri-State Command)

• Analog Select Register (Analog Command)

• Calibration of Timers (Calibration Command)

• Reset (Reset Command)

Figure 6, page 10, is a graphical description of the device

operation in Normal mode. Switch states are latched into the

input register on the falling edge of CS. The INT to the MCU

is cleared on the rising edge of CS. However, INT will not

clear on rising edge of CS if a switch has closed during SPI

communication (CS low). This prevents switch states from

being missed by the MCU.

PROGRAMMABLE SWITCH REGISTER

Inputs SP0 to SP7 may be programmable for switch-to-

battery or switch-to-ground. These inputs types are defined

using the settings command (refer to Table 6). To set an SPn

input for switch-to-battery, a logic [1] for the appropriate bit

must be set. To set an SPn input for switch-to-ground, a

logic [0] for the appropriate bit must be set. The MCU may

change or update the Programmable Switch Register via

software at any time in Normal mode. Regardless of the

setting, when the SPn input switch is closed a logic [1] will be

placed in the Serial Output Response Register (refer to

Table 17, page 19).

Table 6. Settings Command

Settings Command

Not used

Battery/Ground Select

sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0

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