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PC33975A 데이터시트(PDF) 4 Page - Freescale Semiconductor, Inc

부품명 PC33975A
상세설명  Multiple Switch Detection Interface with Suppressed Wake-Up and 32mA Wetting Current
PDF  32 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PC33975A 데이터시트(HTML) 4 Page - Freescale Semiconductor, Inc

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Analog Integrated Circuit Device Data
4
Freescale Semiconductor
33975
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
Figure 3. 33975 Terminal Connections
Table 2. Terminal Definitions
A functional description of each terminal can be found in the Functional Terminal Description section on page 11.
Terminal
Terminal
Name
Formal Name
Description
1
GND
Ground
Ground for logic, analog, and switch-to-battery inputs.
2
SI
SPI Slave In
SPI control data input terminal from MCU to 33975.
3
SCLK
Serial Clock
SPI control clock input terminal.
4
CS
Chip Select
SPI control chip select input terminal from MCU to 33975. Logic [0] allows data
to be transferred in.
5–8
25–28
SPn
Programmable Switches 0–3
Programmable Switches 4–7
Programmable switch-to-battery or switch-to-ground input terminals.
9–15,
18–24
SGn
Switch-to-Ground Inputs 0–6
Switch-to-Ground Inputs 13–7
Switch-to-ground input terminals.
16
VPWR
Battery Input
Battery supply input terminal. This terminal requires external reverse battery
protection.
17
WAKE
Wake-Up
Open drain wake-up output is designed to control a power supply enable
terminal.
29
INT
Interrupt
Open-drain output to MCU is used to indicate input switch change of state.
30
AMUX
Analog Multiplex Output
Analog multiplex output.
31
VDD
Voltage Drain Supply
3.3/5.0 V supply sets SPI communication level for SO driver.
32
SO
SPI Slave Out
Provides digital data from 33975 to MCU.
SO
1
SP7
SP6
SP5
SP4
SG7
SG8
SG9
SG10
SG11
SG13
WAKE
SG12
INT
VDD
AMUX
GND
SP0
SP1
SP2
SP3
SG0
SG1
SG2
SG3
SG4
SG6
VPWR
SG5
CS
SI
SCLK
8
9
10
11
12
13
14
15
16
3
4
5
6
7
2
32
25
24
23
22
21
20
19
18
17
30
29
28
27
26
31



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