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www.diodes.com

April 2019

Diodes Incorporated

PI7C9X760

Document Number DS40305 Rev 6-2

A product Line of

Diodes Incorporated

PI7C9X760

10. I2C-bus Interface

The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-bus interface consists of

two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock and serial data can go up to 100 kbps and

in the Fast-mode, the serial clock and serial data can go up to 400 kbps. The first byte sent by an I2C-bus master contains a start bit

(SDA transition from HIGH to LOW when SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next

byte is the sub-address that contains the address of the register to access. The UART responds to each write with an acknowledge

(SDA driven LOW by UART for one clock cycle when SCL is HIGH). If the TX FIFO is full, the UART will respond with a negative

acknowledge (SDA driven HIGH by UART for one clock cycle when SCL is HIGH) when the CPU tries to write to the TX FIFO.

The last byte sent by an I2C-bus master is a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 8 - 10 below.

For complete details, see the I2C-bus specifications.

SDA

SCL

S

P

START condition

STOP condition

Figure 9. I2C Start and Stop Conditions

S

W

P

SLAVE

ADDRESS

REGISTER

ADRESS

nDATA

White block: host to UART

Grey block: UART to host

A

A

A

S

W

P

SLAVE

ADDRESS

A

S

R

NA

White block: host to UART

Grey block: UART to host

REGISTER

ADRESS

SLAVE

ADDRESS

A

A

A

nDATA

LAST DATA

Figure 10. Master writes to slave (UART)

Figure 11. Master reads from slave (UART)