NRF9160-SICA-R7 datasheet(29/400 Pages) NORDIC

29 / 400 page

Application core

4.3.1.3 RAM[n].POWERCLR (n=0..7)

Address offset: 0x608 + (n × 0x10)

RAMn power control clear register

When read, this register will return the value of the POWER register.

Bit number

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

H G F E

D C B A

Reset 0x0000FFFF

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

R/W

Field

Value ID

Value

Description

A-D W

S[i]POWER (i=0..3)

Keep RAM section Si of RAM n on or off in System ON mode

Off

E-H W

S[i]RETENTION (i=0..3)

Keep retention on RAM section Si of RAM n when RAM section is

switched off

Off

4.4 NVMC — Non-volatile memory controller

The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory

and the user information configuration register (UICR).

The NVMC is a split security peripheral. This means that when the NVMC is configured as non-secure, only

a subset of the registers is available from the non-secure code. See SPU — System protection unit on page

259 and Registers on page 32 for more details.

When the NVMC is configured to be a secure peripheral, only secure code has access.

Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, before

an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG on page

33. The user must make sure that writing and erasing are not enabled at the same time. Failing to do

so may result in unpredictable behavior.

4.4.1 Writing to flash

When writing is enabled, in CONFIG register for secure region, or in CONFIGNS register for non-secure

region, flash is written by writing a full 32-bit word to a word-aligned address in flash.

Secure code has access to both secure and non-secure regions, by using the appropriate configuration of

CONFIG and CONFIGNS registers. Non-secure code, in constrast, has access to non-secure regions only.

Thus, non-secure code only needs CONFIGNS.

The NVMC is only able to write '0' to erased bits in flash, that is bits set to '1'. It cannot write a bit back to

'1'.

As illustrated in Memory on page 21, flash is divided into multiple pages. The same address in flash can

only be written nWRITE number of times before a page erase must be performed.

Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits to flash,

write the data as a word, and set all the bits that should remain unchanged in the word to '1'. Note that

the restriction about the number of writes (see above) still applies in this case.

The time it takes to write a word to flash is specified by tWRITE. If CPU executes code from flash while the

NVMC is writing to flash, the CPU will be stalled.

Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a bus fault.

4418_1315 v2.0

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