SM6802A

NIPPON PRECISION CIRCUITS INC.—2

BLOCK DIAGRAM

PIN DESCRIPTION

Number

*2. Ip = input pin with built-in pull-up resistor

Function

1

LEQP

I

Lch equalizer network connection

2

LIN

I

Lch signal input

3

VDD1

–

Supply (input system)

4

RIN

I

Rch signal input

5

REQP

I

Rch equalizer network connection

6

REQN

I

Rch equalizer network connection

7

VSS1

–

Ground (input system)

8

PDWN

I

Power-down control (active LOW)

9

DRCN

I

Dynamic range compression mode setting (HIGH: normal operation, LOW: compression mode)

10

ROUTN

O

Rch speaker minus (–) output

11

VDD2

–

Supply (output stage)

12

ROUTP

O

Rch speaker plus (

+) output

13

VSS2

–

Ground (output stage)

14

LOUTP

O

Lch speaker plus (

+) output

15

VDD3

–

Supply (output stage)

16

LOUTN

O

Lch speaker minus (–) output

17

MUTEN

I

Mute control (active LOW)

18

TESTN

Ip

Test pin (HIGH: normal operation, LOW: test mode)

19

VREF1

–

Reference voltage 1 (bias voltage)

20

LEQN

O

Lch equalizer network connection

LIN

VSS2

VDD2

LOUTP

VDD1

VSS1

PWM

Modulator

VDD3

LEQP

DRCN

TESTN

LEQN

MUTEN

PWDN

MUTE,POWERDOWN,

PROTECTION

BUFFER

VREF1

RIN

REQP

REQN

BIAS

VREF

PWM

Modulator

+

−

+

−

+

−

+

−

OSC

LEVEL SHIFTER

LOUTN

BUFFER

LEVEL SHIFTER

ROUTP

BUFFER

LEVEL SHIFTER

ROUT

BUFFER

LEVEL SHIFTER