AP32113

Connecting Memory to the TC1130 External Bus Unit

(EBU)

Application Note

30

V1.0, 2006-02

3.7

Register settings for various SDRAM Devices

3.7.1

Registers Independent of Device Type

3.7.1.1

EBUCON - EBU Configuration Register

Table 7

EBUCON Register Settings

3.7.1.2

BUSCONx - EBU Bus Configuration Register

Table 8

BUSCON Register Settings

SDRMRE

F

REFRESHC Number of clock cycles

between refresh operations

Tref in device data sheet

REFRESHR Number of refresh command Refer to device data sheet

1) The terms used in this column are based on the Intel PC SDRAM Specification, Revision 1.7 except T

ref.

Registers

Setting

Function

EBU_CON

0x04F9 FF68

1:1 mode, clock gating on

0x00F9 FF681)

1) The option is fastest setting and verified on TC1130 Triboard

1:1 mode, clock gating off

0x05F9 FF68

1:2 mode, clock gating on

0x01F9 FF68

1:2 mode, clock gating off

Registers

Setting

Function

BUSCON

0x30700000

SDRAM Type 0 & 16 bit port width

0x30B00000

Prefetch Off, SDRAM Type 0 & 32 bit

port width

0x40700000

SDRAM Type 1 & 16 bit port width

0x40B00000

SDRAM Type 1 & 32 bit port width

0x30B400001)

1) The option is fastest setting and verified on TC1130 Triboard

Prefetch On, SDRAM Type 0 & 32 bit

port width

Table 6

The relationship between register definition and parameters

Register

Bit Field

Function Description

Corresponding to1)