MPC8540 datasheet(206/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

4-20

Freescale Semiconductor

Reset, Clocking, and Initialization

4.4.3.15 PCI Debug Configuration

The PCI debug configuration input, shown in Table 4-23, enables PCI/PCI-X debug mode. In this

mode, source ID information is driven onto the highest order address bits PCI_AD[62:58] during

the bus command phase (PCI) or attribute phase (PCI-X). Note that the value latched on this signal

during POR is accessible through the PORDBGMSR described in Section 18.4.1.5, “POR Debug

Mode Status Register (PORDBGMSR).”

4.4.3.16 PCI-X Configuration

The PCI-X configuration input, shown in Table 4-24, configures PCI or PCI-X mode on the

PCI/PCI-X port. Note that this input does not support the three states of the PCIXCAP input

defined in the PCI-X specification. It is sampled as either a 1 or a 0 during reset only. Note that the

value latched on this signal during POR is accessible through the memory-mapped PORDEVSR,

described in Section 18.4.1.4, “POR Device Status Register (PORDEVSR).”

4.4.3.17 Memory Debug Configuration

The memory debug configuration input, shown in Table 4-25, selects which debug outputs (DDR

or LBC memory controller) are driven onto the MSRCID and MDVAL debug signals. Note that

the value latched on this signal during POR is accessible through the memory-mapped

Table 4-22. PCI Arbiter Configuration

Functiona

Signal

Reset

Configuration

Name

Value

(Binary

)

Meaning

PCI_GNT2

cfg_pci_arbiter

The on-chip PCI/PCI-X arbiter is disabled. External arbitration is required.

Default (1)

The on-chip PCI/PCI-X arbiter is enabled (default).

Table 4-23. PCI Debug Configuration

Functiona

l Signal

Reset Configuration

Name

Value

(Binary)

Meaning

PCI_GNT3

Default (1)

cfg_pci_debug

PCI debug is enabled. Source ID information is driven onto the highest

order address bits, PCI_AD[62:58], during the bus command phase

(PCI) or attribute phase (PCI-X).

PCI operates in normal mode (default)

Table 4-24. PCI/PCI-X Configuration

Functional

Signal

Reset Configuration

Name

Value

(Binary)

Meaning

PCI_GNT4

Default (1)

cfg_pci_mode

PCI-X mode

PCI mode (default)

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