MPC8540 datasheet(9/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

5.8

Interrupts and Exception Handling ................................................................................ 5-20

5.8.1

Exception Handling ................................................................................................... 5-20

5.8.2

Interrupt Classes ........................................................................................................ 5-21

5.8.3

Interrupt Types ........................................................................................................... 5-21

5.8.4

Upper Bound on Interrupt Latencies ......................................................................... 5-22

5.8.5

Interrupt Registers...................................................................................................... 5-22

5.9

Memory Management.................................................................................................... 5-24

5.9.1

Address Translation ................................................................................................... 5-26

5.9.2

MMU Assist Registers (MAS1–MAS4 and MAS6) ................................................. 5-27

5.9.3

Process ID Registers (PID0–PID2)............................................................................ 5-27

5.9.4

TLB Coherency.......................................................................................................... 5-27

5.10

Memory Coherency ....................................................................................................... 5-28

5.10.1

Atomic Update Memory References ......................................................................... 5-28

5.10.2

Memory Access Ordering.......................................................................................... 5-28

5.10.3

Cache Control Instructions ........................................................................................ 5-28

5.10.4

Programmable Page Characteristics .......................................................................... 5-29

5.11

Core Complex Bus (CCB) ............................................................................................. 5-29

5.12

Performance Monitoring................................................................................................ 5-29

5.12.1

Global Control Register ............................................................................................. 5-30

5.12.2

Performance Monitor Counter Registers ................................................................... 5-30

5.12.3

Local Control Registers ............................................................................................. 5-30

5.13

Legacy Support of PowerPC Architecture..................................................................... 5-31

5.13.1

Instruction Set Compatibility..................................................................................... 5-31

5.13.1.1

User Instruction Set ............................................................................................... 5-31

5.13.1.2

Supervisor Instruction Set...................................................................................... 5-31

5.13.2

Memory Subsystem ................................................................................................... 5-32

5.13.3

Exception Handling ................................................................................................... 5-32

5.13.4

Memory Management................................................................................................ 5-32

5.13.5

Reset........................................................................................................................... 5-32

5.13.6

Little-Endian Mode.................................................................................................... 5-33

5.14

PowerQUICC III Implementation Details ..................................................................... 5-33

Chapter 6

Core Register Summary

6.1

Overview.......................................................................................................................... 6-1

6.1.1

Register Set .................................................................................................................. 6-1

6.2

6.2.1

Special-Purpose Registers (SPRs) ............................................................................... 6-4

6.3

Registers for Computational Operations.......................................................................... 6-8

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