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MPC8540 데이터시트(PDF) 249 Page - Freescale Semiconductor, Inc |
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MPC8540 데이터시트(HTML) 249 Page - Freescale Semiconductor, Inc |
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249 / 1302 page ![]() PowerQUICC III Implementation Details MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 5-35 PIR value The PIR value is all zeros on PowerQUICC III devices. PVR value The PVR reset value is 0x8020_nnnn. See Table 5-1. PVR[VERSION] = 0x8020 PVR[REVISION] = 0xnnnn (revision specific value) SVR value The SVR reset value is0x8030_nnnn. See Table 5-1. SVR[VERSION] = 0x8030 SVR[REVISION] = 0xnnnn (revision specific value) Table 5-8. Differences Between the e500 Core and the PowerQUICC III Core Implementation (continued) Feature PowerQUICC Implementation |
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