MPC8540 datasheet(104/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

1-10

Freescale Semiconductor

Overview

— Completion and refetch serialization control

— Synchronization for all instruction flow changes—interrupts and mispredicted branches

•

Two simple execution units that perform the following:

— Single-cycle add and subtract

— Single-cycle shift and rotate

— Single-cycle logical operations

— Supports integer signal processing operations

•

Multiple-cycle execution unit (MU)

— Four-cycle latency for integer and floating-point multiplication (including integer,

fractional, and both vector and scalar floating-point multiply instructions).

— Variable-latency divide: 4, 11, 19, and 35 cycles for all Book E, SPE, and SPFP divide

instructions. Note that the MU allows divide instructions to bypass the second two MU

pipeline stages, freeing those stages for other MU instructions to execute in parallel.

— Four-cycle floating-point multiply

— Four-cycle floating-point add and subtract

•

Signal processing engine APU (SPE APU). The SIMD capability provided by the 64-bit

execution units (MIU, LSU, SIU1) is not a separate execution unit. The hardware that

executes 32-bit Book E instructions also executes the lower half of 64-bit SPU instructions.

— Single-cycle integer add and subtract

— Single-cycle logical operations

— Single-cycle shift and rotate

— Four-cycle integer pipelined multiplies

— 4-, 11-, 19-, and 35-cycle integer divides

— Four-cycle single instruction multiple data (SIMD) pipelined multiply-accumulate

(MAC)

— 64-bit accumulator for MAC operations

— Single-precision floating-point operations

•

Load/store unit (LSU)

— Three-cycle load latency

— Fully pipelined

— Four-entry load queue allows up to four load misses before stalling

— Can continue servicing load hits when load queue is full

— Six-entry store queue allows full pipelining of stores

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