MPC8540 datasheet(113/1302 Pages) FREESCALE

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MPC8540 Architecture Overview

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

1-19

packet-switched system-level interconnect that can be used in a variety of applications as an open

standard. The RapidIO architecture provides a rich variety of features including high data

bandwidth, low-latency capability, and support for high-performance I/O devices, as well as

providing message-passing and software-managed programming models.

The RapidIO unit on the MPC8540 supports the I/O and message-passing logical specifications,

the common transport specification, and the 8/16 LP-LVDS physical layer specification of the

RapidIO Interconnect Specification. It does not support the globally shared memory logical

specification.

Highlights of the implementation include: support for four priority levels and ordering within a

priority level, CRC error management, 32- to 256-byte transactions and 8-bit data width ports.

The physical layer of the RapidIO unit can operate at up to 500 MHz. Because the interface is

defined as a source-synchronous, double-data-rate, LVDS-signaling interconnect, the theoretical

unidirectional peak bandwidth is 8 Gbps. Receive and transmit ports operate independently,

resulting in an aggregate theoretical bandwidth of 16 Gbps.

1.3.14.1 RapidIO Message Unit

The MPC8540’s RapidIO messaging supports one inbox/outbox structure for data and one

doorbell structure for messages. Both chaining and direct modes are provided for the outbox, and

messages can hold up to 16 packets of 256 bytes, or a total of 4 Kbytes.

1.3.15 Power Management

In addition to low-voltage operation and dynamic power management in its execution units, the

MPC8540 supports four power consumption modes: full-on, doze, nap, and sleep. The three

low-power modes: doze, nap, and sleep, can be entered under software control in the e500 core or

by external masters accessing a configuration register.

Doze mode suspends execution of instructions in the e500 core. The core is left in a standby mode

in which cache snooping and time base interrupts are still enabled. Device logic external to the

processor core is fully functional in this mode.

Nap mode shuts down clocks to all the e500 functional units except the time base, which can be

disabled separately. No snooping is performed in nap mode, but the device logic external to the

processor core is fully functional.

Sleep mode shuts down not only the e500 core, but all of the MPC8540 I/O interfaces as well. Only

the interrupt controller and power management logic remain enabled so that the device can be

awakened.

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