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Address Translation and Mapping

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

2-3

(CCSRBAR).” However, note that the e500 core only provides one default TLB entry to access

boot code and it allows for accesses within the highest 4 Kbytes of memory. In order to access the

full 8 Mbytes of default boot space (and the 1 Mbyte of CCSR space), additional TLB entries must

be set up within the e500 core for mapping these regions.

2.2

Address Translation and Mapping

Four distinct types of translation and mapping operations are performed on transactions in the

MPC8540. These are as follows:

•

Mapping a local address to a target interface

•

Assigning attributes to transactions

•

Translating the local 32-bit address to an external address space

•

Translating external addresses to the local 32-bit address space

The local access windows perform target mapping for transactions within the local address space.

No address translation is performed by the local access windows.

Outbound ATMU windows perform the mapping from the local 32-bit address space to the address

spaces of RapidIO or PCI/PCI-X, which may be much larger than the local space. Outbound

ATMU windows also map attributes such as transaction type or priority level.

Inbound ATMU windows perform the address translation from the external address space to the

local address space, attach attributes and transaction types to the transaction, and also map the

transaction to its target interface. Note that in mapping the transaction to the target interface, an

inbound ATMU window performs a similar function as the local access windows. The target

mappings created by an inbound ATMU must be consistent with those of the local access

windows. That is, if an inbound ATMU maps a transaction to a given local address and a given

target, a local access window must also map that same local address to the same target.

All of the configuration registers that define translation and mapping functions use the concept of

translation or mapping windows, and all follow the same register format. Table 2-3 summarizes

the general format of these window definitions.

Windows must be a power-of-two size. To perform a translation or mapping function, the address

of the transaction is compared with the base address register of each window. The number of bits

used in the comparison is dictated by each window’s size attribute. When an address hits a

Table 2-3. Format of ATMU Window Definitions

Function

Translation address

High-order address bits defining location of the window in the target address space

Base address

High-order address bits defining location of the window in the initial address space

Window size/attributes

Window enable, window size, target interface, and transaction attributes

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