MPC8540 datasheet(169/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

3-1

Chapter 3

Signal Descriptions

This chapter describes the MPC8540 external signals. It is organized into the following sections:

•

Overview of signals and cross-references for signals that serve multiple functions,

including two lists: one by functional block and one alphabetical

•

List of reset configuration signals

•

List of output signal states at reset

NOTE

A bar over a signal name indicates that the signal is active low, such

as IRQ_OUT (interrupt out). Active-low signals are referred to as

asserted (active) when they are low and negated when they are high.

Signals that are not active low, such as IRQ (interrupt input), are

referred to as asserted when they are high and negated when they are

low.

Internal signals throughout this document are shown as lower case and

in italics. For example, sys_logic_clk is an internal signal. These are

referenced only as necessary for understanding of the external

functionality of the device.

3.1

Signals Overview

The MPC8540 signals are grouped as follows:

•

DDR memory interface signals

•

RapidIO interface signals

•

PCI/PCI-X interface signals

•

Ethernet management interface signals

•

TSEC1 interface signals

•

TSEC2 interface signals

•

FEC10/100 interface signals

•

Local bus interface signals

•

DMA interface signals

•

PIC interface signals

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