MPC8540 datasheet(199/1302 Pages) FREESCALE

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Functional Description

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

4-13

4.4.3.2

e500 Core PLL Ratio

Table 4-10 describes the e500 core clock PLL inputs that program the core PLL and establish the

ratio between the e500 core clock and the e500 core complex bus (CCB) clock. There is no default

value for this PLL ratio; these signals must be pulled to the desired values. Note that the values

latched on these signals during POR are accessible through the memory-mapped PORPLLSR, as

described in Section 18.4.1.1, “POR PLL Status Register (PORPLLSR),” and also in the e500 core

HID1 register, as described in Section 6.10.2, “Hardware Implementation-Dependent Register 1

(HID1).”

Table 4-9. CCB Clock PLL Ratio

Functional Signals

Reset Configuration

Name

Value

(Binary)

CCB Clock : SYSCLK Ratio

LA[28:31]

No default

cfg_sys_pll[0:3]

0000

16 : 1

0001

Reserved

0010

2 : 1

0011

3 : 1

0100

4 : 1

0101

5 : 1

0110

6 : 1

0111

Reserved

1000

8 : 1

1001

9 : 1

1010

10 : 1

1011

Reserved

1100

12 : 1

1101

Reserved

1110

Reserved

1111

Reserved

Table 4-10. e500 Core Clock PLL Ratios

Functional Signals

Reset Configuration

Name

Value (Binary)

e500 Core: CCB ClockRatio

LALE, LGPL2

No default

cfg_core_pll[0:1]

2 : 1

5 : 2 (2.5:1)

3 : 1

7 : 2 (3.5:1)

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